1. Field of the Invention
The present invention relates to an active matrix type display.
2. Description of the Related Art
An active matrix type display supplies respective image signals to separated pixel electrodes through switching elements such as thin film transistors (TFTs). Deterioration of the liquid crystal of such an active matrix type display is commonly prevented by driving the display using an alternating current (AC) driving configuration in which alternating potential is applied to an opposite electrode and supplementary capacities of the display. Meanwhile, electric power consumption of the display is often conserved by decreasing an electric potential difference between the positive polarity and the negative polarity of a video signal to be input into the drain driver of the display, and by decreasing the current and voltage of the drain driver.
There is also known a method referred to as horizontal inversion opposite AC driving in which the polarities of a video signal to be supplied to each drain line are inverted at every horizontal period. However, because in the horizontal inversion opposite AC driving the polarities of the voltages of the opposite electrode and all of the supplementary capacity lines are inverted every horizontal period, capacitive loads in the opposite electrode and in all of the supplementary capacity lines remain large, the electrical power consumption also remains great.
To attempt to further decrease the electrical power consumption, a further driving method, hereinafter referred to as “SC driving”, is known. In SC driving, the electrical power consumption can be remarkably decreased by inverting the polarities of the voltages of the supplementary capacities and by setting the voltage of the opposite electrode to be a fixed voltage. SC driving also decreases the current and the voltage of the drain driver by decreasing the potential difference between the positive polarity and the negative polarity of a video signal. In the following, an active matrix type liquid crystal display employing SC driving will be described.
FIG. 11 is an equivalent circuit diagram of a display panel of an active matrix type liquid crystal display employing SC driving. A plurality of drain lines 105 are arranged along vertical directions, and a plurality of gate lines 107 are arranged along horizontal directions. At the intersections of the drain lines 105 and the gate lines 107, TFTs 109 being switching elements are provided.
The gates of the TFTs 109 are connected to the gate lines 107, and the drains of the TFTs 109 are connected to the drain lines 105. The sources of the TFTs 109 are connected to electrodes on one side of liquid crystal capacities 112. The remaining electrodes, those on the other side of the liquid crystal capacities 112, constitute an opposite electrode 111, which is integrally formed with a substrate arranged on the opposite side of another substrate, on which the TFTs 109 are formed, with liquid crystal sandwiched the substrates.
Moreover, capacity electrodes on one side of supplementary capacities 110 are connected to the sources of the TFTs 109. The electrodes on the other side of the supplementary capacities 110 are connected to supplementary capacity lines 108. The supplementary capacity lines 108 are formed in parallel with the gate lines 107, and are commonly connected to a plurality of the supplementary capacities 110 aligned in row directions.
FIG. 12 shows signal waveforms for driving one pixel in a display panel. FIG. 12 shows a gate voltage VG, a pixel voltage VP, a source voltage VS, a video signal voltage VD, a supplementary capacity voltage VSC and an opposite electrode voltage VCOM. The gate voltage VG has one period each frame.
In an on period of gates, the gate voltage VG to be applied to a gate line 107 takes a high (hereinafter referred to as “High”) level. During this period, TFTs 109 connected to the gate line 107 are turned on, and the drains of the TFTs 109 conduct to the gates of the TFTs 109. The source voltages Vs then follow the video signal voltages VD, which are applied to the drain lines 105, to assume levels equal to those of the video signal voltages VD. Then, the source voltages VS are applied to the capacity electrodes on one side of the liquid crystal capacities 112 and the supplementary capacities 110 which are arranged at the row of the selected gate line 107. When the operation enters into a gate off period, the gate voltage VG becomes a low (hereinafter referred to as “Low”) level, and the TFTs 109 are turned off. Then, the source voltages VS are determined, and descend in level by a voltage .VS accompanying the falling of the gate voltage VG to be a voltage VPL.
The opposite electrode voltage VCOM is a fixed voltage. The level of the opposite electrode voltage VCOM is lowered from the center levels VC of the video signal voltages VD by the amount of the descended voltage .VS of the source voltages VS.
The supplementary capacity voltages VSC are applied to each supplementary capacity line 108. The levels of the supplementary capacity voltages VSC are inverted after the gate voltage VG applied to a corresponding gate line 107 falls. The supplementary capacity voltages VSC are severally inverted between two levels of a high level VSCH and a low level VSCL. For example, in a positive polarity period, in which the source voltages VS are higher than the opposite electrode voltage VCOM, the supplementary capacity voltages VSC rise from their low levels VSCL to their high levels VSCH after the falling of the gate voltage VG. Consequently, the pixel voltages VP are obtained by the temporary determination of the source voltages VS after the falling of the gate voltage VG. After that, the obtained pixel voltages VP severally ascend by a voltage .VP owing to an influence of the rising of the supplementary capacitor voltages VSC through the supplementary capacities 110. The pixel voltages VP at this time are held during the off period of the gates, i.e. within the frame period.
As described above, because of the rises in the supplementary capacity voltages VSC, charges are reallocated between the liquid crystal capacities 112 and the supplementary capacities 110. Then, the pixel voltages VP ascend by the voltage .VP=VPH−VPL. In a negative polarity period, in which the source voltages VS are lower than the opposite electrode voltage VCOM, the supplementary capacity voltages VSC inversely fall from their positive sides to their negative sides. Consequently, the pixel voltages VP severally descend by the voltage .VP. As a result, the amplitudes of the pixel voltages VP become larger, which makes it possible to enlarge the voltage to be applied to the liquid crystal 112.
That is, by inverting the supplementary capacity voltages VSC between the two levels severally, it becomes possible to make the amplitudes of the video signal voltages VD small for applying sufficient voltages to the liquid crystal capacities 112 even if the opposite electrode voltage VCOM is a direct-current voltage.
Because the supplementary capacities 110 are ordinarily sufficiently larger than the liquid crystal capacities 112, the amounts of changed voltages .VP of the pixel voltages VP are controlled in response to the variation voltages V (VSCH−VSCL) of the supplementary capacity voltages VSC for each line. Accordingly, by varying the supplementary capacity voltages VSC of the supplementary capacity lines 108, large voltages can be applied to the liquid capacities 112. In other words, by varying the supplementary capacity voltages VSC, it is possible to make the amplitudes of the video signal voltages VD small.
As the number of pixels in typical displays has increased, additional methods have been employed to deal with the increase. On such method involves simultaneously switching on a plurality of drain lines, and then applying the video signal voltages VD to a plurality of the liquid crystal capacities 112 and the supplementary capacities 110 simultaneously. Thereby, it becomes possible to secure sufficient time for the drain lines 105 to apply the video signal voltages VD to the liquid crystal capacities 112 and the supplementary capacities 110.
In particular, when a display panel large in size or highly fine in display quality is dot-sequentially driven, several tens of the drain lines 105 are turned on at the same time, and the video signals VD are applied to several tens of the liquid crystal capacities 112 and the supplementary capacities 110 at the same time. When several tens of the drain lines 105 are simultaneously turned on in this manner, a large capacity coupling is generated at parts where the ON drain lines 105 are superposed on the supplementary capacity lines 108. The voltages of the supplementary capacity lines 108 and the gate lines 107 are influenced by the voltages of the drain lines 105 through the capacity coupling. Because of the voltage changes, nonuniformity of an image is sometimes generated for every group of drain lines 105 which are turned on at the same time.